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  cmlt5554 surface mount silicon dual, complementary high voltage transistor the central semiconductor cmlt5554 consists of one 2n5551 npn silicon transistor and one individual isolated complementary 2n5401 pnp silicon transistor, manufactured by the epitaxial planar process and epoxy molded in an sot-563 surface mount package. this device has been designed for high voltage amplifier applications. marking code: 5c4 sot-563 case maximum ratings: (t a =25c) symbol npn (q1) pnp (q2) units collector-base voltage v cbo 180 160 v collector-emitter voltage v ceo 160 150 v emitter-base voltage v ebo 6.0 5.0 v continuous collector current i c 600 ma power dissipation p d 350 mw operating and storage junction temperature t j , t stg -65 to +150 c thermal resistance ja 357 c/w electrical characteristics: (t a =25c unless otherwise noted) npn (q1) pnp (q2) symbol test conditions min max min max units i cbo v cb =120v - 50 - - na i cbo v cb =100v - - - 50 na i cbo v cb =120v, t a =100c - 50 - - a i cbo v cb =100v, t a =150c - - - 50 a bv cbo i c =100a 180 - 160 - v bv ceo i c =1.0ma 160 - 150 - v bv ebo i e =10a 6.0 - 5.0 - v v ce(sat) i c =10ma, i b =1.0ma - 0.15 - 0.2 v v ce(sat) i c =50ma, i b =5.0ma - 0.2 - 0.5 v v be(sat) i c =10ma, i b =1.0ma - 1.0 - 1.0 v v be(sat) i c =50ma, i b =5.0ma - 1.0 - 1.0 v h fe v ce =5.0v, i c =1.0ma 80 - 50 - h fe v ce =5.0v, i c =10ma 80 250 60 240 h fe v ce =5.0v, i c =50ma 30 - 50 - f t v ce =10v, i c =10ma, f=100mhz 100 300 100 300 mhz c ob v cb =10v, i e =0, f=1.0mhz - 6.0 - 6.0 pf h fe v ce =10v, i c =1.0ma, f=1.0khz 50 200 40 200 nf v ce =5.0v, i c =200a, r s =10, f=10hz to 15.7khz - 8.0 - 8.0 db r3 (29-june 2015) www.centralsemi.com
cmlt5554 surface mount silicon dual, complementary high voltage transistor lead code: 1) emitter q1 2) base q1 3) collector q2 4) emitter q2 5) base q2 6) collector q1 marking code: 5c4 sot-563 case - mechanical outline pin configuration www.centralsemi.com r3 (29-june 2015)
cmlt5554 surface mount silicon dual, complementary high voltage transistor services ? bonded inventory ? custom electrical screening ? custom electrical characteristic curves ? spice models ? custom packaging ? package base options ? custom device development / multi discrete modules (mdm?) ? bare die available for hybrid applications limitations and damages disclaimer: in no event shall central be liable for any collateral, indirect, punitive, incidental, consequential, or exemplary damages in connection with or arising out of a purchase order or contract or the use of products provided hereunder, regardless of whether central has been advised of the possibility of such damages. excluded damages shall include, but not be restricted to: cost of removal or reinstallation, rework, ancillary costs to the procurement of substitute products, loss of profits, loss of savings, loss of use, loss of data, or business interruption. no claim, suit, or action shall be brought against central more than two (2) years after the related cause of action has occurred. in no event shall centrals aggregate liability from any warranty, indemnity, or other obligation arising out of or in connection with a purchase order or contract, or any use of any central product provided hereunder, exceed the total amount paid to central for the specific products sold under a purchase order or contract with respect to which losses or damages are claimed. the existence of more than one (1) claim against the specific products sold to buyer under a purchase order or contract shall not enlarge or extend this limit. buyer understands and agrees that the foregoing liability limitations are essential elements of a purchase order or contract and that in the absence of such limitations, the material and economic terms of the purchase order or contract would be substantially different. www.centralsemi.com r3 (29-june 2015)


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